A core cell is essentially a standard part, or subroutine, for use in a VLSI design. A VLSI designer uses a core cell in much the same way that a board level designer uses an off-the-shelf IC when designing a PC board, or the way a software engineer might call a library subroutine.
At Jacobs Pineda, Inc., we use the core cell methodology to deliver our VLSI designs to our licensees. This methodology enables VLSI designers to combine their proprietary designs with designs from Jacobs Pineda, Inc. to create highly integrated and portable VLSI systems with a minimum of design effort and silicon cost.
We deliver our core cells in a design kit consisting of:
- Core cell netlist synthesized to your target library in Verilog format
- Stand-alone test shell
- Bit-accurate simulator (Solaris/Linux executable)
- Verification test vectors
- User's Specification and Manual
- Synopsys logic library
- Synopsys models for RAM and ROM blocks
- Verilog simulation models for logic, RAM, and ROM
The design kit is intended to be used with Synopsys Design Compiler, the Synopsys VCS Verilog simulator, and a Solaris workstation or Linux workstation. Use of other tools may require some customer modification of the design kit deliverables. Compiled Synopsys VMC models may be provided under special request to support higher speed simulation.
STANDALONE SIMULATION ENVIRONMENT
The design kit allows the core cell to be simulated and verified in a stand-alone environment prior to integration with customer designed circuitry. This allows the customer to become familiar with the JPI core cell operation before designing interface logic. Further, the stand-alone environment can also be helpful in isolating problems during system level simulation by providing a reference for the behavior of the core cell.
The stand-alone environment works by comparing the reference bit-accurate algorithic simulator written in the C language with the netlist level simulation. The bit-accurate simulator is written to model the numeric behavior of the core cell output, and also at internal intermediate points in the computation. Comparing the bit-accurate simulation against the netlist simulation gives a very high degree of confidence that the core cell is operating correctly.
CORE CELL DESIGN FLOW
The design kit components are used by the customer to incorporate the core cell into the customer's VLSI design. The customer combines their proprietary RTL or netlist level designs with the JPI netlist to synthesize a full chip level netlist. For verification, the customer combines their test environment with JPI test shell components and the bit accurate simulator to produce a system level simulation that can verify the JPI core cell in the customer's system environment.
MANUFACTURING TEST
JPI core cells are primarily intended to work with a Scan Test methodology. The customer is responsible for inserting scan test circuitry during the layout phase, and for generating manfacturing test vectors.